【MEMSマイクアレイ】 データ収集システム 同期信号の追加

-- Package for Array signal processing
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package ARRAY_PKG is
  constant N_CH : integer := 12; -- Maximum number of channels,最大チャンネル数
        -- Actual number of mic-channel must be less than or equal to N_CH
		
constant N_BYTE : integer := 1; -- Bytes of data, 扱うデータのバイト数
  subtype SIG is std_logic_vector (N_BYTE*8-1 downto 0);-- one unit of data
  
  -- Signal for microphone input
  type SIG_ARRAY is array (0 to N_CH-1) of SIG;
  
  -- Buffer signal with additional channel for frame synchronization 
  type BUF_ARRAY is array (-1 to N_CH-1) of SIG;
  
  -- Multiplexed microphone signal with L/R switching 
  subtype MEMSIG is std_logic_vector (N_BYTE*4-1 downto 0); 
  type MEMSIG_ARRAY is array(0 to N_CH-1) of MEMSIG;
  
end ARRAY_PKG;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.ARRAY_PKG.all;

ENTITY MEMS_IN IS
	PORT(
			memsin 		:  	in 	MEMSIG_ARRAY;
			mic   		:  	out SIG_ARRAY;
			reset     	:  	in 	STD_LOGIC;
			clk			:  	in 	STD_LOGIC
		 );
END MEMS_IN;

ARCHITECTURE behavior OF MEMS_IN IS
	signal regN : MEMSIG_ARRAY;
BEGIN
PROCESS(clk,reset) 
BEGIN
	IF(reset = '0')THEN
		regN <= (others => (others =>'0'));
		mic <= (others => (others =>'0'));
		ELSIF(clk'EVENT AND clk = '1')THEN
			for n in 0 to N_CH -1 loop
				for m in N_BYTE*4 -1 downto 0 loop
					mic(n)(2*m)   <= regN(n)(m);
					mic(n)(2*m+1) <= memsin(n)(m);
				end loop;
			end loop;
			ELSIF(clk'EVENT AND clk = '0')THEN
				for n in 0 to N_CH -1 loop 
					regN(n) <= memsin(n);
				end loop; 
	END IF;		
END PROCESS;
END behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.ARRAY_PKG.all;

ENTITY CHANNEL_SELECTOR IS
	PORT(
			out_data	:  	out	SIG;
			in_data   	:  	in 	BUF_ARRAY;
			Ch_cnt		:  	in 	SIGNED(4 downto 0);
			clk_60MHz  	:	in 	STD_LOGIC
		 );
END CHANNEL_SELECTOR;

ARCHITECTURE behavior OF CHANNEL_SELECTOR IS
	signal count : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

PROCESS(Ch_cnt,in_data,clk_60MHz) 
BEGIN
	IF(clk_60MHz'EVENT AND clk_60MHz ='1')THEN
		out_data <= in_data(conv_integer(Ch_cnt));
	END IF;
END PROCESS;

END behavior;

-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
-- Module  Version: 5.8
--D:\lscc\diamond.12\ispfpga\bin\nt64\scuba.exe -w -n FIFO8to8 -lang vhdl -synth lse -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 16384 -width 8 -rwidth 8 -no_enable -pe 0 -pf 0 

-- Mon Oct 24 11:22:45 2022

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
-- synopsys translate_on

entity FIFO8to8 is
    port (
        Data: in  std_logic_vector(7 downto 0); 
        WrClock: in  std_logic; 
        RdClock: in  std_logic; 
        WrEn: in  std_logic; 
        RdEn: in  std_logic; 
        Reset: in  std_logic; 
        RPReset: in  std_logic; 
        AmEmptyThresh: in  std_logic_vector(13 downto 0); 
        AmFullThresh: in  std_logic_vector(13 downto 0); 
        Q: out  std_logic_vector(7 downto 0); 
        Empty: out  std_logic; 
        Full: out  std_logic; 
        AlmostEmpty: out  std_logic; 
        AlmostFull: out  std_logic);
end FIFO8to8;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_textio.all;
LIBRARY STD;
USE std.textio.all;
USE work.ARRAY_PKG.all;

-- TOP Level Hardware 
ENTITY recording_mic IS 
	PORT(
			clk_60MHz	: in 		STD_LOGIC; -- Clock from FT232H USB interface
			mic_clk		: buffer 	STD_LOGIC; -- Clock for MEMS Mic
			memsin		: in 		MEMSIG_ARRAY; -- Connect to MEMS Mic
			                        -- SIG_ARRAY dimension is set in ARRAY_PKG.vhd
			RESET_SW   	: in  		STD_LOGIC; -- Connect to tact switch1
			START_SW	: in  		STD_LOGIC; -- Connect to tact switch2
			word_out  	: out 		STD_LOGIC_VECTOR(N_BYTE*8-1 downto 0);
			                        -- send to USB UART/FIFO IC (FT232H)
		--  Controll Signals(Flag signals with FT232H)
			WR			: out		STD_LOGIC; 
			TXE			: in		STD_LOGIC;
			RD			: out		STD_LOGIC;
			RXF			: in		STD_LOGIC;
		--  Signals for  monitoring internal state
			LED 		: out 		STD_LOGIC_VECTOR(7 downto 0)
	     );
END recording_mic; 

ARCHITECTURE behavioral OF recording_mic IS
    signal mic_in  	: SIG_ARRAY; -- Mic slgnal from MEMS_IN
	signal clk_3MHz	: STD_LOGIC; -- Clock
	signal mclk_D 	: STD_LOGIC; -- Clock delayed 1 clock cycle 
	signal mclk 	: STD_LOGIC; -- Confirmation output 確認用出力
	signal reset 	: STD_LOGIC;
    signal Ch_cnt	: signed(4 downto 0); -- Channel Counter
	signal Ch_n		: signed(4 downto 0):= "01000"; -- Number of channels
	signal WR_busy	: STD_LOGIC;  -- 1 in write status 書込み状態で1
	signal Samp_cnt	: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; 
	                  -- Time Sample Counter 時間サンプル数のカウント用
	signal Samp_n	: STD_LOGIC_VECTOR(15 downto 0); -- 時間サンプル数の上限
	signal data_cnt	: STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
	signal START_D 	: STD_LOGIC;  -- For START signal generation START生成用
	signal START 	: STD_LOGIC; -- Signal indicating START status
	signal cnt_3M 	: STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
	signal RUN 		: STD_LOGIC := '0'; --  1 in RUN status，動作状態のとき1
	signal in_data_buffer : BUF_ARRAY; -- Input Buffer, size = Ch_n +1
	signal in_data_dummy  : SIG_ARRAY; -- 
	signal mic_data	: STD_LOGIC_VECTOR(N_BYTE*8-1 downto 0);
	-- Built-in FIFO-related signals，FIFO用信号
	signal FIFO_out	: STD_LOGIC_VECTOR(7 downto 0);
	signal FIFO_in 	: STD_LOGIC_VECTOR(7 downto 0); -- to FIFO8to8
	signal out_data	: STD_LOGIC_VECTOR(7 downto 0);
	signal WrEn 	: STD_LOGIC;
	signal WrEnPre 	: STD_LOGIC;
	signal WrEn_D 	: STD_LOGIC;
	signal WrEn1_D 	: STD_LOGIC;
	signal RdEn 	: STD_LOGIC;
	signal RdEn_D 	: STD_LOGIC;
	signal Empty 	: STD_LOGIC;
	signal Full 	: STD_LOGIC;
	signal AmEmpty 	: STD_LOGIC;
	signal AmFull  	: STD_LOGIC;
	signal FIFO_reset  : STD_LOGIC;
	signal RPReset 	   : STD_LOGIC; -- for Read Pointer Reset
	signal AmEmptyThresh : STD_LOGIC_VECTOR(13 downto 0); 
	signal AmFullThresh  : STD_LOGIC_VECTOR(13 downto 0); 
	signal dummy         : BUF_ARRAY;

COMPONENT MEMS_IN IS
	port(
			memsin		:	in	MEMSIG_ARRAY;
			mic			:	out SIG_ARRAY;
			reset		:	in  STD_LOGIC;
			clk			:	in  STD_LOGIC
		);
END COMPONENT;	
	
COMPONENT CHANNEL_SELECTOR
	PORT(
			out_data 	:  	out	SIG; -- Output of selector
			in_data   	:  	in 	BUF_ARRAY;-- Input of selector
			Ch_cnt		:  	in 	SIGNED(4 downto 0);
			clk_60MHz  	:  	in 	STD_LOGIC
		 );		
END COMPONENT;

COMPONENT FIFO8to8
    port (
        Data: in  std_logic_vector(7 downto 0); 
        WrClock: in  std_logic; 
        RdClock: in  std_logic; 
        WrEn: in  std_logic; 
        RdEn: in  std_logic; 
        Reset: in  std_logic; 
        RPReset: in  std_logic; 
        AmEmptyThresh: in  std_logic_vector(13 downto 0); 
        AmFullThresh: in  std_logic_vector(13 downto 0); 
        Q: out  std_logic_vector(7 downto 0); 
        Empty: out  std_logic; 
        Full: out  std_logic; 
        AlmostEmpty: out  std_logic; 
        AlmostFull: out  std_logic
		);
end COMPONENT;

BEGIN	

Mic_signal: MEMS_IN
	PORT MAP(
			memsin		=> memsin,
			mic			=> mic_in,
			reset		=> reset,
			clk			=> clk_3MHz
			);
			
ChSelector: CHANNEL_SELECTOR
	PORT MAP(
				out_data	=> FIFO_in,
				in_data 	=> in_data_buffer,
				clk_60MHz 	=> clk_60MHz,
				Ch_cnt 		=> Ch_cnt   
			 );
			 
FIFO:FIFO8to8
	PORT MAP(
			Data 		=> FIFO_in,
			WrClock 	=> clk_60MHz,
			RdClock 	=> clk_60MHz,
			WrEn 		=> WrEn,
			RdEn 		=> RdEn,
			Reset 		=> FIFO_reset,
			RPReset 	=> RPReset, 
			AmEmptyThresh => AmEmptyThresh,
			AmFullThresh => AmFullThresh,
			Q 			=> word_out,
			Empty 		=> Empty,
			Full 		=> Full,
			AlmostEmpty	=> AmEmpty,
			AlmostFull	=> AmFull
			);
					 
mic_clk	<= clk_3MHz;
mclk 	<= clk_3MHz;
-- FIFO8to8のフラグの閾値を設定
AmEmptyThresh <= CONV_std_logic_vector(128,14); 
AmFullThresh <= CONV_std_logic_vector(2048,14); 
WrEnPre <= RUN AND Wr_busy AND NOT(Full) ;	

PROCESS(clk_60MHz) -- WrEnPreを１クロック遅延した信号を生成
BEGIN
	IF(clk_60MHz'EVENT AND clk_60MHz = '1')THEN
		WrEn <= WrEnPre;
	END IF;
END PROCESS;

-- Connect microphone input to buffer
buffer_gen : for I in 0 to conv_integer(N_CH) - 1 generate
                in_data_buffer(I) <= mic_in(I);
			 end generate;

-- Assign frame sync signal to Ch_n channel, フレーム同期用データを設定
in_data_buffer(conv_integer(-1)) <= "11110000";

PROCESS(clk_60MHz,reset) -- 3MHz clock generation
BEGIN
	IF(reset ='0')THEN
		cnt_3M  <= (others => '0');
		clk_3MHz <='0';
	ELSIF(clk_60MHz'EVENT AND clk_60MHz='1')THEN
		IF(cnt_3M < 19)THEN
			cnt_3M <= cnt_3M + 1;
			IF(cnt_3M < 10)THEN
				clk_3MHz <= '0';
			ELSE
				clk_3MHz <= '1';
			END IF;
		ELSE
			cnt_3M  <= (others => '0');
		END IF;
	END IF;
END PROCESS;

PROCESS(clk_60MHz,START, WR_busy,reset)  -- Ch counter
BEGIN                     -- Count from 0 to Ch_n  
	IF(reset='0' OR START = '0')THEN
		Ch_cnt <= "11111";
	ELSIF(clk_60MHz'EVENT AND clk_60MHz='1' AND WR_busy ='1')THEN
		IF(Ch_cnt = Ch_n-1)THEN
			Ch_cnt <= "11111";
		ELSE
			Ch_cnt <= Ch_cnt + 1;
		END IF;
	END IF; 
END PROCESS;

PROCESS(clk_60MHz, reset)-- Generates a active low write start signal
BEGIN                    --  mclkからLアクティブの書き込みスタート信号を生成
	IF(reset='0')THEN
		mclk_D <= '0';
	ELSIF(clk_60MHz'EVENT AND clk_60MHz='1')THEN
		mclk_D <= mclk;
	END IF;
END PROCESS;
-- Generate a negative pulse at every rising edge of mclk
-- mclkの立上りエッジ毎に負パルスを生成
START <= NOT(mclk AND NOT(mclk_D) AND RUN);

PROCESS(START_SW, reset) -- Generate RUN signal with external switch
BEGIN                     
	IF(reset='0')THEN
		RUN <= '0';
	ELSE
		IF(START_SW = '0')THEN
			RUN <= '1';  -- 一度RUN=1になったらリセットまで1
		END IF;
	END IF;
END PROCESS;

PROCESS(clk_60MHz,reset) --State transition for WR_busy
BEGIN -- FIFO8to8への書き込み許可信号を生成するステートマシン
	IF(reset='0')THEN  -- 書込みビジー状態を表す信号Wr_busyを作る
		WR_busy <= '0';
	ELSIF(clk_60MHz'EVENT AND clk_60MHz='1')THEN
		CASE WR_busy is
		WHEN '0' => -- FIFO8to8がFULLでなければSTART=0で書き込み状態に移行
				IF(START = '0' AND Full = '0')THEN
					WR_busy <= '1';
				ELSE
					WR_busy <= '0';
				END IF;
			WHEN '1' =>  -- Ch_cnt = Ch_n-1になるまで書き込み状態を維持
				IF(Ch_cnt = Ch_n-1)THEN
					WR_busy <= '0';
				ELSE
					WR_busy <= '1';
				END IF;
			WHEN OTHERS =>
					WR_busy <='0';
		END CASE;
	END IF; 
END PROCESS; 

-- WR control　FT232H内蔵のFIFOへの書き込み制御信号WRを生成
-- FT232Hの空きバッファフラグTXE=0かつFIFO8to8の読み出し可能信号RdEn=1のとき0
WR <=	'1' 	WHEN (TXE = '1' OR RdEn ='0') ELSE
		'0' 	WHEN (TXE = '0' AND RdEn = '1');

PROCESS(clk_60MHz,reset) --State transition for RdEn
-- FIFO8to8からのデータ読み出し許可信号RdEnを生成
-- FIFO8to8がFullにならないように制御したい　・・・
BEGIN
	IF(reset='0')THEN
		RdEn <= '0';
	ELSIF(clk_60MHz'EVENT AND clk_60MHz='1')THEN
		CASE RdEn is
			WHEN '0' =>  -- FIFO8to8がAlmostFullになってからRdEn=1とする
				IF(AmFull = '1')THEN
					RdEn <= '1';
				ELSE
					RdEn <= '0';
				END IF;
			WHEN '1' =>  -- FIFO8to8がAlmostEmptyになったらRdEn=0とする
				IF(AmEmpty = '1')THEN
					RdEn <= '0';
				ELSE
					RdEn <= '1';
				END IF;
			WHEN OTHERS =>
					RdEn <='0';
		END CASE;
	END IF; 
END PROCESS;